Fine Grain partial Reconfiguration on ultra ninety six MP SoC

Motivation FPGA technology provides the flexibility of on-site programming and re-programming without going through re-fabrication with a modified design. Partial Reconfiguration (PR) takes this flexibility one step further, allowing the modification of an operating FPGA design

Project Title

Fine Grain partial Reconfiguration on ultra ninety six MP SoC

Project Area of Specialization

Electrical/Electronic Engineering

Project Summary

Motivation
FPGA technology provides the flexibility of on-site programming and re-programming without going through re-fabrication with a modified design. Partial Reconfiguration (PR) takes this flexibility one step further, allowing the modification of an operating FPGA design by loading a partial configuration file, usually a partial BIT file. After a full BIT file configures the FPGA, partial BIT files can be downloaded to modify reconfigurable regions in the FPGA without compromising the integrity of the applications running on those parts of the device that are not being reconfigured.

The logic in the FPGA design is divided into two different types, reconfigurable logic, and static logic. One area of the FPGA block represents static logic and the other block portion represents reconfigurable logic. The static logic remains functioning and is unaffected X-Ref Target. Basic Premise of Partial Reconfiguration FPGA Reconfigure Block A4.bit A3.bit A2.bit A1.bit. The reconfigurable logic is replaced by the contents of the partial BIT file.

Today, with the growing emphasis on deploying Field Programmable Gate Arrays (FPGAs) for computing, we are starting to see FPGA’s reprogram ability being recognized as a deciding feature in selecting FPGAs over ASICs [1]. Yet, partial reconfiguration (PR), which allows parts of an FPGA to be reconfigured at millisecond timescales, remains an under-appreciated capability.

The significant improvements in the performance, logic density, and power efficiency of Field-Programmable Gate Arrays (FPGAs) have made them useful for implementing nearly any type of digital application. In FPGAs, significant improvements will make by optimizing the fine-grained programmable logic and routing architecture of the FPGA.

Project Objectives

The objectives of our project are as follows,

• To learn the architecture of FPGA.
• To Learn the architecture of reconfiguration memory.
• To learn the method of Reverse engineering.
• Reduce the size of the FPGA required to implement a function.
• Consequent reductions in cost and power consumption.

Project Implementation Method

Methodology    

Theoretical Studies

Partial reconfiguration is a design process, which allows a limited, predefined portion of an FPGA to be reconfigured while the rest of the device continues to operate. We can use such a partial bitstream to change the structure of one part of an FPGA design as the rest of the device continues to operate. Partial reconfiguration increases the functionality of a single FPGA, allowing for fewer, smaller devices than would otherwise be needed.

The following terminology is specific to the Partial Reconfiguration feature and it will be used throughout this project.

Bottom-Up Synthesis

Bottom-Up Synthesis is a synthesis of the design by modules, whether in one project or multiple projects. In Vivado, bottom-up synthesis is referred to as out-of-context (OOC) synthesis. OOC synthesis generates a separate netlist (or DCP) file per OOC module and is required for Partial Reconfiguration to ensure no optimization occurs across the module boundary. In OOC synthesis, the top-level (or static) logic is synthesized with black box module definitions for each OOC module.

Configuration

A configuration is a complete design that has one Reconfigurable Module for each

Reconfigurable Partition. There might be many configurations in a Partial Reconfiguration FPGA project. Each configuration generates one full BIT file as well as one partial BIT file for each Reconfigurable Module (RM).

Configuration Frame

Configuration frames are the smallest addressable segments of the FPGA configuration memory space. Reconfigurable frames are built from discrete numbers of these lowest level elements. In Xilinx devices, the base reconfigurable frames are one element (CLB, block RAM, DSP) wide by one clock region high. The number of resources in these frames vary by device family.

Internal Configuration Access Port (ICAP)

The internal configuration access port (ICAP) is essentially an internal version of the Select MAP interface.

Partial Reconfiguration (PR)

Partial Reconfiguration is modifying a subset of logic in an operating FPGA design by downloading a partial bitstream.

Reconfigurable Frame

Reconfigurable frames (in all references other than “configuration frames” in this guide) represent the smallest reconfigurable region within an FPGA. Bitstream sizes of reconfigurable frames vary depending on the types of logic contained within the frame.

Reconfigurable Logic

Reconfigurable logic is any logical element that is part of a reconfigurable module. These logical elements are modified when a partial BIT file is loaded. Many types of logical components can be reconfigured such as LUTs, flip-flops, block RAM, and DSP blocks.

Benefits of the Project

Expected Results

After completing our project, we are expected that out project will

• Able to dynamically modify blocks of logic application by downloading partial bit files while the remaining logic continues to operate without interruption.

• Provide flexibility in the choices of algorithms or protocols available to an application

• Enable new techniques in design security.

• Improve FPGA fault tolerance.

• Accelerate configurable computing.

Technical Details of Final Deliverable

Method of Analysis

Reconfigurable devices struggle with the time needed to load the configuration bitstream. And also for small bitstreams in partially reconfigurable FPGAs this time cannot be ignored. FPGA partial reconfiguration (PR) is a Xilinx design flow that attempts to create reconfiguration regions in an FPGA device so that one region can be reconfigured while the remainder of the FPGA continues to operate in the system. Examples of PR applications and advantages of PR are presented. Analysis of the reconfiguration time is done for partial reconfiguration using the internal reconfiguration port, i.e. ICAP when controlled by the on-chip processor. The results of the analysis of the reconfiguration time and throughput on memory interface width and processor cache are presented and summarized here. Presented work will be supported by performance analysis. We will analyze by seeing when the topologies were chosen whether the cost of the resources, we low or not, or whether the Fan-in was low or not. VIVADO’s design run can be used to analyze the Number of LUTs used, Delay, Power, Latency, Frequency, whether or not the throughout was higher, and accuracy.

The full proposal pdf form is available at 
ttps://drive.google.com/drive/folders/1PGdF5BY5B6SORBqVwkrjhd0vrF95vlhE?usp=sharing

Final Deliverable of the Project

HW/SW integrated system

Core Industry

Education

Other Industries

IT

Core Technology

Robotics

Other Technologies

Others

Sustainable Development Goals

Quality Education

Required Resources

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