Design and Verification of Asynchronous FIFO using System Verilog

Project Title

Design and Verification of Asynchronous FIFO using System Verilog

Project Area of Specialization Electrical/Electronic EngineeringProject Summary

First In First Out (FIFO) is a buffer to store data and retrieve data in a way that stored first comes out of the buffer first. Asynchronous FIFO are most widely used in the System on Chip (SOC) designs for data buffering and flow control. As the System on chip involves multiple Intellectual Property (IPs) operating at different speeds.

 FIFO is an approach for handling program work requests from queues or stacks so that the oldest request is handled first. In hardware, it is either an array of flops or read/write memory that stores data from one clock domain and on request supplies the same data to other clock domains following FIFO logic. An improved technique for FIFO design is to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains and asynchronous to each other. For synchronization purposes Asynchronous FIFO is used when the write operation is faster than the read operation and will affect the operation on the chip. 

Our project work for Asynchronous FIFO includes the complete layout structure and functional verification through (SV) system verilog. The creation of testbench includes the environment that is implemented through various testing.

FIFO architectures inherently have a challenge of synchronizing itself with the pointer logic of other clock domains and controlling the read and write operation of FIFO memory locations safely with the user logic. Data is written into the FIFO by the write clock domain and data is read from the FIFO by the read clock domain where the two clock domains are asynchronous to each other.

FIFO module is to understand the hierarchical architecture of design we specify this design under configuration Asynchronous module under (VMM) Verifications Methodology Manual, (UVM) Universal Verification Methodology and OMM ……….etc. Many More components are built to check the validity of asynchronous FIFO.

Project Objectives

Verification is the most important aspect of the product development process and it consumes as much as 80% of the total product development time. The intention is to verify that the design meets the system requirements and specifications. Approaches to design verification consist of logic simulation/emulation and circuit simulation, in which detailed functionality and timing of the design are checked means of simulation/emulation.

This project included the design and functional verification of Asynchronous FIFO. We created a complete verification environment using System Verilog (SV) which consisted of creation of all the classes like transaction, generator, driver, monitor, scoreboard, environment and top test bench. 

FIFO Using Different Read and Write Logics Design where data values are written sequentially into a FIFO buffer using one clock domain, and the data values are sequentially read from the same FIFO buffer using another clock domain.

The objectives of this project are :

• To gain a better understanding of the architecture of a synchronous FIFO module

• To design a configurable Asynchronous FIFO module under various specifications like UVM, VMM, OVM……..

• To verify the Asynchronous FIFO module design using UVM and SystemVerilog.

• To validate the verification environment through testing.

• To obtain the functionality verification of Asynchronous FIFO with a high level of coverage results.

Project Implementation Method

The verification of the Asynchronous FIFO design is carried out to check if the design is working as per the specification.

Modules are generated to check the functionality of the asynchronous FIFO Design.

The Verification Methodology includes the various modules are generated to check the functionality of Asynchronous FIFO design  and these are following:

Interface 

This component is responsible for driving signals to the DUT. It receives data items

repeatedly from the Sequencer and subsequently drives signals to the DUT.The interface consists of a bundle of wires i.e. multiple signals used to connect the Testbench to the DUT.

Testcase

This Component verifies the pattern and checks the functionalities of design.The test case module will instantiate the environment module and call the methods in the environment.

Transaction:

 This component is responsible for creating different meaningful tests for the DUT. These tests are basically the inputs given to the DUT. The inputs to the DUT are called as data items.

Driver:

It is used to drive signals to DUT using a virtual interface.The driver block receives the transactions from the mailbox mbx and assigns the values in the transaction to the individual signals of the DUT through virtual interfaces. 

Monitor:

This component is responsible for sampling the DUT signals without driving them. It collects coverage details and does checking.This is the receiver section that receives the data from the receiver side of the Asynchronous FIFO.

ScoreBoard:

It will receive the transaction from agents and compare the DUT output with expected values to check the correctness of DUT.

Environment :

The environment happens to be the top-level component in a verification test bench. It contains all the verification components. It also contains configuration properties that allow customization of topology and behavior, making it reusable.

FIFO is verified using UVM test bench, the simulation is carried out. The scoreboard results are obtained by comparing actual data and expected data, if the data matches, successfully compared will be displayed in transcript or else mismatch will be displayed.

Verification Test Bench

Benefits of the Project

Asynchronous FIFO design uses a different technique (also derived from synchronous FIFO design) of using an additional bit in the FIFO pointers to detect full and empty. In this scheme, full and empty is determined by comparing the read and write pointers. The write pointer always points to the next location to be written; the read pointer always points to the current FIFO entry to be read. On reset, both pointers are reset to zero. The FIFO is empty when the two pointers (including the extra bit) are equal.

Asynchronous FIFOs are used to safely pass data from one clock domain to another clock domain. There are many ways to do asynchronous FIFO design, including many wrong ways. Most incorrectly implemented FIFO designs still function properly 90% of the time.This FIFO pointer convention has the added benefit of low access latency. As soon as data has been written, the FIFO drives read data to the FIFO data output port, hence the receive side does not need to use two clocks (first set a read enable, then read the data) to read out the data.

Technical Details of Final Deliverable

The Proposed work gives the complete framework and draft outlet of the chip synthesis and GDSII file. It is verified successfully and able to be produced in FAB industries. All the status will be verified in it.Verifications were carried out in VHDL, Verilog and SystemVerilog.

High-level data types are missing from VHDL and Verilog. Technique for controlling is a more advanced version of Verilog that employs more complex principles. The natural process for developing a UVM verification environment is bottom-up. 

The Generator class is in charge of creating the stimulus by randomizing the transaction class and then passing the randomized class to drive.The transaction class declares the fields needed to produce the stimulus. The transaction class may also be used to represent the activity that the monitor on DUT signals is monitoring and the driver class converts the processes generated by the device into realistic DUT inputs. 

The interface connects the driver with the DUT. The same packet is sent to the Scoreboard for verification. Agents are also linked to other modules in this component, such as the scoreboard, Mailbox, Generator, and Driver are all part of the Environment container class. The Mailbox is created, and the mailbox handle is passed between the generator and the driver.

UVM is designed to enable the production of strong, reusable, and compatible verification IP and test bench components, and it reflects the latest advances in verification technology. Its programming language is Verilog. UVM Class Library gives you the tools you need to easily create well-built and well reusable verification components and test environments. UVM test bench is used to verify the SoC and also used to simulate it.

Final Deliverable of the Project HW/SW integrated systemCore Industry TelecommunicationOther Industries Education , Manufacturing , Others Core Technology Internet of Things (IoT)Other Technologies Artificial Intelligence(AI), Robotics, OthersSustainable Development Goals Quality Education, Industry, Innovation and InfrastructureRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	31000
Panaflex Sheet	Miscellaneous	2	1800	3600
Standies	Miscellaneous	2	2000	4000
E Fabless Submission Fee	Equipment	1	7000	7000
Workshop Tour IC Design Tools	Equipment	2	2000	4000
Workshop Verification of Chip through verilog	Equipment	2	3000	6000
Workshop Tour IC Design Tools	Equipment	2	3200	6400