Design and Implementation of a Fault Tolerant RISC V Architecture on FPGA

Project Title

Design and Implementation of a Fault Tolerant RISC V Architecture on FPGA

Project Area of Specialization Electrical/Electronic EngineeringProject Summary

Processors in space face unique challenges due to the effects of high radiations. Devices and processors used in such critical conditions require high level of protection and security. Keeping this scenario in mind, we aim to design a processor with fault tolerant capability. Our approach to this problem is based on designing and implementing a RISC-V Processor on FPGA and make it fault-tolerant. The key features of our solution include the implementation of RISC-V on FPGA which offers the advantage of reduced and simple instructions set. Developing a fault-tolerant ALU for architecture is another key feature for error-less applications.
The major technical challenges include understanding and simulating Verilog design of RISC-V architecture on Modelsim and further implementing it on FPGA. In future, we are expecting challenges in designing the error detection strategy for fault tolerant architecture and Software development for the final design.
 

Project Objectives

Digital systems are vulnerable to run-time faults because of external conditions which alter the functionality of the circuit. There is a need of designing a fault-tolerant and self-healing architecture along with implementation of a soft-core processor for sensitive applications which involve highly classified data.
 

Project Implementation Method

• Implementation of RISC-V processor is done on Zedboard (FPGA) using Vivado (software).
• Fault-tolerant architecture is implemented using the same software (vivado).
• Automatic Partial reconfiguration for multiple bit error removal is done by designing application specific PR controller.
• Communication with FPGA using software is developed on Python with the help of Tkinter toolkit.

Benefits of the Project

There are several advantages of a fault-tolerant architecture in number of industries.

• The defence industry is a sensitive department which requires both a fault-tolerant architecture, and the FPGA integrated with RISC-V open instruction set architecture (ISA). Therefore, there is a need to design a fault-tolerant RISC-V architecture and implement it on FPGA
• This novel approach will also enable the educational institutes to perform quality research using the way forward.

Technical Details of Final Deliverable

The functionality of our final design would be to incorporate bit errors occurring inside ALU. Developing a software is also a part of our final design whose functionality would be to communicate with FPGA for sending instructions. The technical details of final product are that it would be able to:

• Receive instruction(s) from a computer software.
• Process received instruction(s) based on RISC-V architecture implemented on it.
• Each instruction is 32-bits wide.
• The instructions are in little endian format, that is, least significant value in the sequence is stored first at the lowest storage address.
• The instruction set is limited to and, or, add, subtract, load, store, and multiply.
• If instructions are received continuously, it processes them in a pipelined manner.
• The ALU unit of the processor would be fault-tolerant. That is, if a bit-error occurs in the ALU unit, it configures it by using the Redundant modules and Partial Reconfiguration technique.
• After processing the instructions, it displays the memory elements on host computer so that user can observe the changes.

There are certain limitations of our final product which include:

• The fault-tolerant capability will be incorporated in just one block of the processor, which is ALU block.
• The fault tolerant approach is only valid if there is a single bit error in the module. If two or more than two bits are changed simultaneously, there is a possibility that the error is not detected.
• If a fault arises in error detection circuitry, there is no way to remove that error by partial recon?guration.
• The fault-tolerant approach is only valid for single event upset (SEU).
• If two single-bit errors (of the same bits) occur simultaneously in original and error detection LUT, then it would not be detected.

Final Deliverable of the Project HW/SW integrated systemCore Industry OthersOther IndustriesCore Technology OthersOther TechnologiesSustainable Development Goals Industry, Innovation and InfrastructureRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	70000
Zedboard	Equipment	1	70000	70000