RISC-V open source chip design and FPGA Validation

Project Title

RISC-V open source chip design and FPGA Validation

Project Area of Specialization Electrical/Electronic EngineeringProject Summary

RISC-V is an open-source and royalty-free ISA standard that relies on the RISC architecture. This means that the hardware is less complicated, and the instruction set contains fewer instructions, compared to a CISC architecture. However, on average more instructions are needed per computer program.

Project Objectives

In terms of ISA design, RISC-V is reaching a mature and stable state only by now [Waterman et al. 2014]. RISC-V was developed in 2010, but the user-level ISA base and extensions MAFDQ (Multiply/divide, Atomic, single-precision Floating-point, Double-precision floating-point and Quadruple-precision floating-point: the main standard exten-sions) were frozen only in 2014 [RV-foundation 2018a]. For the privileged ISA, at the time of this writing, it is still a draft, albeit at an advanced stage. For the physical imple-mentations, there are several open-sourced RISC-V CPU designs available.

RISC-V comprises of a base user-level 32-bit integer instruction set. Called RV32I, it includes 47 instructions, which can be grouped into six types:

R-type: register-register

I-type: short immediates and loads

S-type: stores

B-type: conditional branches, a variation of S-type

U-type: long immediates

J-type: unconditional jumps, a variation of U-type

Project Implementation Method

Micro-architecture design and analysis of a RISC-V instruction set processor has been articulated in this paper. Instruction Set Architectures (ISAs) for processors from Intel, AMD, Intel, MIPS etc. is protected through IP Rights and Infringements. Few ISAs do exist as open-source viz. Open RISC, SPARC, RISC-V etc. RISC-V ISA has been evolved from the efforts at University of California, Berkeley and has been open sourced as BSD license. This paper details the microarchitecture design and analysis of a 5-stage pipelined RISC-V ISA compatible processor and effects of instruction set on the pipeline / micro-architecture design. The design have been analyzed in terms of instructions encoding, functionality of instructions, instruction types, decoder logic complexity, data hazard detection, register file organization and access, functioning of pipeline, effect of branch instructions, control flow, data memory access, operating modes and execution unit hardware resources. The processor has been micro-architected, simulated using Blue-spec System Verilog, synthesized and analyzed on FPGA platform and 65nm and 130nm technology nodes for ASIC. The synthesis results are compared and analyzed with similar efforts on RISC-V ISA based processor core.

Benefits of the Project

RISC-V is having the attention globally from the industry and academia. Thus, it is prob-able that RISC-V is going to have a significant impact in the future of IoT and cloud. However, by now, there is no RISC-V emulation with low overhead available. In this work, we demonstrated that RISC-V is an architecture that enables its code to be trans-lated into high-quality x86 and ARM code. An strong evidence that DBT engines with high-performance can be built for RISC-V. We did this by building a RISC-V static trans-lator which is able to translate RISC-V to x86 and ARM with an execution overhead

lower than 12% in the former and 35% in the latter, being the fastest RISC-V emulator presented so far in the literature.

Technical Details of Final Deliverable   .As directed by our respected Sir (Dr.anees ullah) to find someone abroad and  convince them to buy you a ( ULTRA 96-V2 ) development board or ( PYNQ-Z2 FPGA ) development board.

we  contacted with one of my neighbor to buy us a ( Ultra 96-V2 )Development board. He is currently in America

And he replied  : 

 That buying a board is a little expensive  for me he added also if I buy it then sending the board will take time because the american govt has a special requirements for these electronics devices and they didn't allow a direct send of these board without am NOC certificate Also because i am new here and didn't knows someone near..

So sending will take time so only option we left are buying it online.

( ULTRA 96-V2 ) development board on buying it online within 10-15 days it costs 80k+ with delivery

( PYNQ-Z2 FPGA ) development board on buying it online within 10-15 days it costs 40k+ with delivery  

In a group chat on whatsapp we decided- it according to our financial and income condition right now that we are able to buy ( PYNQ-Z2 FPGA ) development board instead of ( ULTRA 96-V2 ) development board

Current prices

( PYNQ-Z2 FPGA ) development board

( ULTRA 96-V2 ) development board

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Final Deliverable of the Project Hardware SystemCore Industry OthersOther IndustriesCore Technology Internet of Things (IoT)Other TechnologiesSustainable Development GoalsRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	50000
( PYNQ-Z2 FPGA ) development board	Equipment	2	25000	50000