Implementation of eight bit pipelined microprocessor on FPGA

In order to design a microprocessor, first we will examine the sequence of operations during execution of instructions. Then we will describe the nature of the hardware required to accomplish the instruction execution. In general, any microprocessor works in the following manner: 1.

Project Title

Implementation of eight bit pipelined microprocessor on FPGA

Project Area of Specialization

Electrical/Electronic Engineering

Project Summary

In order to design a microprocessor, first we will examine the sequence of operations during execution of instructions. Then we will describe the nature of the hardware required to accomplish the instruction execution. In general, any microprocessor works in the following manner:

1. The processor fetches an instruction.

2. It decodes the instruction that was fetched. Decoding means identifying what the instruction is.

3. It reads the operands and executes the instruction. For a RISC ISA, for arithmetic instructions, the operands are in registers. The registers that contain the input operands are called source registers. For memory access instructions, addresses are computed using registers and memory is accessed. After execution, the processor writes the result of the instruction execution into the destination. The destination is a register for all instructions other than the store instruction, which has to write the result into the memory.

Hence, the design must contain a unit to fetch the instructions, a unit to decode the instructions, an arithmetic and logic unit (ALU) to execute the instructions, a register file to hold the operands, and the memory that stores instructions and data.

Instruction Fetch Unit

In general, a microprocessor has a special register called the program counter (PC), which points to the next instruction in the instruction memory (or in the instruction caches). The PC sends this address to the instruction memory, which sends the instruction back. The processor increments the PC to point to the next instruction to be fetched. The appropriate target addresses are computed and fed to the PC. A multiplexer is used to select between the branch target, jump target, jump register target, or PC + 4, depending on the instruction.

There are several choices as to when the target addresses are computed. The default target, PC + 4, can be computed at instruction fetch itself, since it needs no information other than the PC itself. In conditional branch instructions, the branch target (PC_Branch) computation can be done as soon as the instruction is read; however, whether the branch is taken or not will not be known until the registers are read and compared. In the case of the jump instruction, the target (PC_Jump) can be computed as soon as the instruction is fetched, since the information for the target is available in the instruction itself. In a jump register (jr) instruction, the branch target (PC_JR) can be computed after the register is read.

Instruction Decode Unit

The opcode is used to identify the instruction and the instruction format used by the instruction. The uniformity of the instruction format allows many of the instruction fields to be directly used for register addressing and control-signal generation. The instruction opcode bits are fed to a control unit that generates the various control signals

Project Objectives

To implement 8-bit pipelined microprocessor

Pipelining is a general technique for improving design timing and hardware utilization efficiency by using parallel units that simultaneously process the output of preceding stages of the pipeline.

• Implementing combinational logic using pipelines can significantly reduce the critical path delay.
• Pipelining can shorten the critical path and improve the throughput (possibly) at a cost of an increased latency between the input-output

Project Implementation Method

The features of the MIPS Processor are verified by Using simulation and prototyping for FPGA.  FPGA Prototyping can be done after the completion of a valid functional simulation and post route simulation. The MIPS processor layout is targeted at Xilinx AES-ULTRA 96-V2 Developmental Board for implementation with FPGA.

Benefits of the Project

Microcontrollers and Microprocessors are used for a number of different types of applications. People may be the most familiar with the desktop PC, but the fact is that desktop PCs make up only a small fraction of all microprocessors in use today. We will list here some of the basic uses for microprocessors:

Signal Processing

Signal processing is an area that demands high performance from microcontroller chips to perform complex mathematical tasks. Signal processing systems typically need to have low latency, and are very deadline driven. An example of a signal processing application is the decoding of digital television and radio signals.

Real Time Applications

Some tasks need to be performed so quickly that even the slightest delay or inefficiency can be detrimental. These applications are known as "real time systems", and timing is of the upmost importance. An example of a real-time system is the anti-lock braking system (ABS) controller in modern automobiles.

Throughput and Routing

Throughput and routing is the use of a processor where data is moved from one particular input to an output, without necessarily requiring any processing. An example is an internet router, that reads in data packets and sends them out on a different port.

Sensor monitoring

Many processors, especially small embedded processors are used to monitor sensors. The microprocessor will either digitize or filter the sensor signals, or it will read the signals and produce status outputs (the sensor is good, the sensor is bad). An example of a sensor monitoring processor is the processor inside an antilock brake system: This processor reads the brake sensor to determine when the brakes have locked up, and then outputs a control signal to activate the rest of the system.

Technical Details of Final Deliverable

The instruction pipelining is a technique that is used to execute multiple instructions parallel with a delay of one clock cycle. The advantage of this technique is that it allows a faster throughput. In pipelining, the instruction execution is usually divided into stages. The number of stages vary depending on implementation. In our case, we have six stage pipelined structure. The instruction is split into multiple steps which can be executed in parallel and the instructions can be processed concurrently, i.e. starting one instruction before finishing the previous one. Pipelining increases the instruction throughput, but does not reduce latency, i.e. the time needed to complete a single instruction. Rather, pipelining may increase the latency due to additional overhead by breaking the computation into separate steps, and depending on how often the pipeline stalls, or needs to be flushed. There are 3 types of hazards that occur while implementing pipelining:

· Structural hazard When a machine is pipelined, the overlapped execution of instructions require the pipelining of functional units and duplication of resources to allow all possible set of instructions in the pipeline. If some combination of instructions cannot be accommodated because of a resource conflict, the machine is said to have a structural hazard.

· Data hazard Data hazard occurs when a current instruction needs the resource and previous instruction is still under execution. Data stalling and forwarding technique is used to prevent data hazard.

· Control hazard If jump or branch instruction occurs, the already fetched instructions after jump or branch needs to be flushed. This decreases the throughput which is a control hazard. The six stage pipeline that is implemented, eliminates the two hazards, structural and data hazard. The structural hazard is eliminated by using two separate memories: instruction memory and data memory. The problem of Data hazard is solved by introducing stalling and forwarding logic

Final Deliverable of the Project

HW/SW integrated system

Core Industry

IT

Other Industries

Core Technology

Others

Other Technologies

Sustainable Development Goals

Industry, Innovation and Infrastructure

Required Resources

If you need this project, please contact me on contact@adikhanofficial.com