FPGA based acceleration of Image Edge detection algorithm

Edge detection is one of the fundamental operations in computer vision. It refers to the process of identifying abrupt changes in pixel intensities in an image. The edges are basic features of an image which can be utilized in  a number of tasks including including image analysis, patt

Project Title

FPGA based acceleration of Image Edge detection algorithm

Project Area of Specialization

Artificial Intelligence

Project Summary

Edge detection is one of the fundamental operations in computer vision. It refers to the
process of identifying abrupt changes in pixel intensities in an image. The edges are basic features of an image which can be utilized in  a number of tasks including including image analysis, pattern recognition, object detection and biomedical etc. The present research in this domain has focused on increasing the accuracy and noise immunity of edge detection algorithms. However, their computational complexity has also increased significantly. The core operation in edge detection is 2D convolution of the filter
kernel with the image. In convolutional neural networks, the computational complexity of convolutional layer is directly proportional to the image size, filter kernel size and number of filters. Consequently, simple software implementation of such algorithms suffers from poor latency and
throughput. This becomes a major limiting factor for applications with high resolution images
and real time requirements. Field Programmable Gate Arrays (FPGAs) are a suitable candidate
to implement most image processing algorithms, thanks to their re-programmability, hardware
parallelism and low development cost as compared to dedicated ASICs. This project proposes a design of  am efficient hardware
accelerator for real time video edge detection using high level synthesis (HLS) desing flow on Xilinx Zynq System
on Chip (SOC) platform. The edge detection accelerator is implemented on the programmable
logic (PL) part of FPGA and integrated as an IP core with the Zynq programmable system (PS).
The accuracy and computational speed of proposed hardware acceleration  system is evaluated and compared with CPU based edge detection. The deliverable of this project is a fully synthesizable IP core of edge
detection system with the hardware software documentation.

Project Objectives

The core objectives of this project are as follows.

1) Applying the capabilities of Xilinx High Level Synthesis design flow to solve computationally intensive image processing task.

2) Development of a synthesizable IP core of image edge detection algorithm using HLS.

3) Functional simulation and cosimulation of IP core on image dataset

4) Selection of suitable interfaces to integrate the IP core with ARM Processing System of Zynq System on Chip.

5) Writing the software device drivers and system level routines to perform real time edge detection on video frames.

Project Implementation Method

The project activity is planned to proceed as follows.

1) Literature review of all the image edge detection methods and kernels are suitable for efficient hardware implementation.

2) Identification and approximation of edge detection kernels based on the available dataset.

3) Software profiling of edge detection solution 

4) Investigating the Xilinx Vivado HLS platform along with OpenCV library integration

5) Development of an IP core for adaptive edge detection.

6) RTL simulation and co simulation of developed IP core

7) Packing and Exporting the IP core in Vivado Design Integrator 

8) System level integration of IP core, required interfaces for image/video acquisition and display and Zynq Programmable System.

9) Synthesis of solution

10) Writng the software drivers of developed system in SDK

11) Real time edge detection

12) Testing and performance estimation.

Benefits of the Project

1) Edge detection is the key algorithm used in video segmentation and object recognition. The core of edge detection is 2D convolution of image with filter kernel. The classical software based implementation of edge detectors offers limited throughput. The GPUs offer the speedup but suffer from huge power consumption. FPGAs are attractive for such applications. However, the classical way of RTL based design of IP accelerators is a very tedious task because it requires to change the RTL code with change in filter kernels  and image resolution. So this project aims at developing an efficient edge detection system using High Level Synthesis design flow which offers design flexilibility.

The FPGA based edge detection system can be utilized in a number of embedded applications including video surveilance, object recognition and filtering.

Since 2D convolution is a core operation in Convolutional Neural Networks, the proposed solution can also be used to accelerate Machine learning algorithms especially deep neural networks with offline transfer learning.

Technical Details of Final Deliverable

The final deliverable of this project would be a fully working, real time image/video edge detection accelerator system. 

The accelerator shall be able to perform real time edge detection from an incomming video stream (of given resolution) coming from a camera, and edge detected image/video to be displayed on the display unit.

The Processing System of Zynq SoC shall be interfaced with the HLS developed IP core. And it shall take the user commands and coefficients of various filters for adaptive edge detection.

Final Deliverable of the Project

Hardware System

Core Industry

Security

Other Industries

IT , Medical , Agriculture

Core Technology

Artificial Intelligence(AI)

Other Technologies

Big Data

Sustainable Development Goals

Industry, Innovation and Infrastructure

Required Resources

If you need this project, please contact me on contact@adikhanofficial.com