Efficient low-latency hardware accelerator for high frequency trading on FPGAs

With huge investments from China in the Economic and infrastructural front, Pakistan is heading towards an astounding growth. Not to forget the investments in CPEC corridor and Gwadar port have already crossed $ 70 Billion, which is more than 25% of their GDP ($ 240 Billion).

Such investments had a huge impact on the capital markets of Pakistan which made it the 2nd best performing stock market in Asia after India. Trading volumes have increased manifold and a lot of Chinese firms have started to put in hot money (FII investments) in Pakistan Stock Exchange (PSE). This provides a perfect opportunity to help Pakistani current market traders to make better decision and help make Pakistan prosper financially.

We are developing a hardware accelerator using FPGA for accelerating high frequency trading (HFT). In this project, we will extract data from Live exchange markets through some built-in libraries or through APIs, the extracted data then will be captured through ethernet cable of FPGA. After the exchange, market data will be sent to FPGA. We will apply a mix of algorithms on the data, the algorithms will make the decision of whether to buy or sell the market data according to the market condition. After the FPGA decide of whether to buy or sell, the order then send back to the market, the time between extracting data and sending back to market is called latency. We will reduce the latency to a very high extent because high frequency is a game of latency. The clients which make a fast decision will be in high profit as compare to the one which have high latency.

Modern financial instrument exchanges provide updates on the current state of the marketplace to their members. This is performed by transmitting messages describing change events on a dedicated ‘market data feed’. These events include changes such as completed trades, bid/ask prices, and other status information. The event messages are typically aggregated into one large market data feed, containing information about all activities within an exchange or market. However, this feed is already in the gigabit range, and members face the problem of parsing this huge volume of data, while also supporting a sub-millisecond response to messages of interest.

Existing pure software solutions are no longer able to provide low latency solutions, so there is a need for hardware acceleration of market feed data processing. Field Programmable Gate Arrays (FPGAs) provide a very attractive means of acceleration, as they are a mature technology, with low power and space requirements. Therefore, our project aim is to design a hybrid type hardware accelerator for HFT using FPGA in order to reduce the latency as much as possible.

The main objectives of this project are:

• Analyze software-based trading.
• Designing hybrid type FPGA base hardware accelerator for High Frequency Trading (HFT).
• Reducing the latency up to a minimum and increase throughput.
• Develop a product based on hardware accelerator in FPGA.

At the least, a high frequency trading (HFT) system architecture always include:

• Input – live market data
• Output – trading orders

• Trading strategy – trading algorithms

Our proposed model will include the above steps, but we will implement our model through the following steps:

1. Testing through python (software base approach)

1. Extracting data from forex market through python.
2. Applying some algorithms through python and comparing with the live market indicators.

1. Extracting Forex Data through python

We extract Forex Data from DUKASCOPY (SWISS BANKING

GROUP) by using Dukascopy library.

   2. Applying Algorithms

We then apply already implemented algorithms on our data such as moving average, RSI, MACD etc. in python just for testing purpose.

      Actual Implementation in FPGA:

The actual implementation in FPGA will be done through the following steps:

1. Market data extracting on FPGA
2. Capturing the data through ethernet port of FPGA
3. Market data decoding on FPGA
4. Applying algorithms on data in FPGA to decide when to buy and sell.
5. Encoding and Sending order back to the trading market

1. Market data extracting on FPGA:

    The first step is to make a connection with a live trading market through APIs, so as that market will update you with the current situation of exchange market through FIX or FAST PROTOCOL. So this way, we will extract the market data on FPGA using APIs.

     2. Data capturing through ethernet port:

   Now as we make a connection with live trading market, the market will update us with the current situation       through some protocol. After extracting the exchange market data, the extracted data then will be captured Through ethernet port of FPGA.         

     3. Market data decoding on FPGA:

 We will propose a scalable architecture for low latency market-data

 decoding. As most of the stock data is encoded in the form of FAST protocol so, we will design a decoding engine which will decode the stock data.

      4.  Applying some sort of Algorithms on market data:

        After the data capture through ethernet port, we will apply hybrid algorithms on the market data which will decide whether to buy or sell the stock automatically according to the market condition and it will automatically generate the order.

   5. Encoding and sending order back to trading market:

After deciding whether to buy or sell the stock, the order then will be encoded and will send back to trading market from where the data was extracted.

As Pakistan is a less developed country. We still utilize the traditional method (software based) of buying and selling of stock market is used, which introduce high and unpredictable processing latencies. 

The speed of market data processing is a key factor to grab the gains and losses of instant trading profits. In our project, we will propose a scalable hardware architecture for low-latency market-data processing on Field Programmable Gate Array (FPGA). Our Project has several benefits in Pakistan, such as

• Adding liquidity to the market
• Algorithmic trading also allows for faster and easier execution of orders, making it attractive for exchanges. In turn, this means that traders and investors can quickly book profits off small changes in price. 
• Increasing trading volume.

The final deliverables are divided into Hardware and Software components:

Hardware Deliverables:

A fully developed hardware product (PAK HFT) based on Zynq System on Chip (SOC) that provides a generic platform for High Frequency Trading (HFT). This product will be highly desirable to Financial industry to accurately predict the market with minimum Latency and high Throughput.

This platform will enable us with

• A generic way to extract and filter incoming traffic using a Pre-processor.
•  Apply a set of trading options that suit our need using a Software/ Hardware codesign approach.
• Incorporate machine learning and artificial intelligence-based trading techniques in hardware.
• Compare the hardware data with the software data in Python/ C++.
• Based on strategy that decides when to buy and sell the stock, send the decision back to the stock market. This will be handled by Port-processor.

Software Deliverables:

We will develop our own propriety trading software implemented in Python/ C++. It will help Trade users in

• Fast implementation of trading strategies.
• Coming up with optimal strategies that suits a user need.
• Applying Data analytics and stock prediction using machine learning and artificial intelligence approaches to trading algorithms that are now most influential in trading market.
• Verification of hardware solution by comparing it with the software tool.

Modern financial instrument exchanges provide updates on the current state of the marketplace to their members. This is performed by transmitting messages describing change events on a dedicated ‘market data feed’. These events include changes such as completed trades, bid/ask prices, and other status information. The event messages are typically aggregated into one large market data feed, containing information about all activities within an exchange or market. However, this feed is already in the gigabit range, and members face the problem of parsing this huge volume of data, while also supporting a sub-millisecond response to messages of interest.

Existing pure software solutions are no longer able to provide low latency solutions, so there is a need for hardware acceleration of market feed data processing. Field Programmable Gate Arrays (FPGAs) provide a very attractive means of acceleration, as they are a mature technology, with low power and space requirements. Therefore, our project aim is to design a hybrid type hardware accelerator for HFT using FPGA in order to reduce the latency as much as possible.

The main objectives of this project are:

• Analyze software-based trading.
• Designing hybrid type FPGA base hardware accelerator for High Frequency Trading (HFT).
• Reducing the latency up to a minimum and increase throughput.
• Develop a product based on hardware accelerator in FPGA.