Domain Specific Customization for RISC-V

This is an FPGA based project which mainly aims to optimize digital accelerator hardware for CNN (convolution neural networks). It is continuation of an earlier project which implemented an accelerator but had some limitations. The main areas to have emphasis on are to improve memory traffic time op

Project Title

Domain Specific Customization for RISC-V

Project Area of Specialization

Electrical/Electronic Engineering

Project Summary

This is an FPGA based project which mainly aims to optimize digital accelerator hardware for CNN (convolution neural networks). It is continuation of an earlier project which implemented an accelerator but had some limitations. The main areas to have emphasis on are to improve memory traffic time optimization by using DMA (Direct memory access), as well as, to make architecture more generic. Lastly, if time allows, we intend to add software support to make porting CNN architectures easier.

Project Objectives

• Generic implementation of CNN accelerator on RISCV

• Optimizing memory reads/writes overhead

• Simplify porting process

Project Implementation Method

Project is divided into following steps

• Develop understanding of RISCV architecture

• Develop understanding of CNN architectures

• Understand existing CNN accelerator implementation

• Improve memory read/write times by designing and implementing AXI DMA

• Implement AXI master to read/write DDR memory

• Modify AXI master to transfer arrays

• Implement complete DMA and test standalone

• Test DMA by programming from RISCV

• Improve existing CNN accelerator design to support different network sizes

• Identify current architecture’s limitations

• Design hardware to be more general

• Implement CNN using new architecture (with DMA and generic hardware)

• Improve software routines to make porting easier

• Report writing

Benefits of the Project

• The design can be used as an architecture to cater needs of AI on the edge market.

• Indigenous development of processors and AI accelerators is critical for different national level products where security is important

Technical Details of Final Deliverable

CNN accelerator for RISCV ported on FPGA with DMA implementation and improved hardware design.

Final Deliverable of the Project

HW/SW integrated system

Core Industry

Education

Other Industries

Core Technology

Others

Other Technologies

Artificial Intelligence(AI)

Sustainable Development Goals

Industry, Innovation and Infrastructure

Required Resources

If you need this project, please contact me on contact@adikhanofficial.com