9T IMC SRAM IP DESIGN

Project Title

9T IMC SRAM IP DESIGN

Project Area of Specialization Electrical/Electronic EngineeringProject Summary

In-memory multiplication followed by accumulation operation capable of

performing MAC (Multiply and accumulate) within 9T SRAM without any changes to the standard

bit cell. The proposed 9T IMC SRAM architecture is capable of performing same operations as

traditional 6T SRAM cells but with better energy consumption and improved delay

Project Objectives

The project objectives are as follows :

- To create a power efficient design

-DSCH3 file

-Timing details

-Datasheet containing all necessary information 

Project Implementation Method

As the project can be divided into two parts. 

1- combinational logic

2- sequential logic 

After performing required transistor sizing methods and finalising the cell structure. 

the combinational part particularly the array design and cell structure will be created on Cadence Virtuoso. 

Along side the sequential part which will be done on modelsim. 

Benefits of the Project

Commonly used SRAM configurations

are 6T,7T,8T but 9T SRAM architecture enables complete data isolation from the bit lines through

this leakage path/ discharge path is eliminated. This arrangement increases the data read and write

stability alongside reducing the power loss and improving the data retention rate.

Technical Details of Final Deliverable

1: Size : 32kBits

2: Area optimized desigb

3: 95nm pdk library

Final Deliverable of the Project Software SystemCore Industry ITOther IndustriesCore Technology Artificial Intelligence(AI)Other TechnologiesSustainable Development Goals Industry, Innovation and InfrastructureRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	65000
Graphic card	Equipment	1	65000	65000