In-memory multiplication followed by accumulation operation capable of performing MAC (Multiply and accumulate) within 9T SRAM without any changes to the standard bit cell. The proposed 9T IMC SRAM architecture is capable of performing same operations as traditional 6T SRAM cell
9T IMC SRAM IP DESIGN
In-memory multiplication followed by accumulation operation capable of
performing MAC (Multiply and accumulate) within 9T SRAM without any changes to the standard
bit cell. The proposed 9T IMC SRAM architecture is capable of performing same operations as
traditional 6T SRAM cells but with better energy consumption and improved delay
The project objectives are as follows :
- To create a power efficient design
-DSCH3 file
-Timing details
-Datasheet containing all necessary information
As the project can be divided into two parts.
1- combinational logic
2- sequential logic
After performing required transistor sizing methods and finalising the cell structure.
the combinational part particularly the array design and cell structure will be created on Cadence Virtuoso.
Along side the sequential part which will be done on modelsim.
Commonly used SRAM configurations
are 6T,7T,8T but 9T SRAM architecture enables complete data isolation from the bit lines through
this leakage path/ discharge path is eliminated. This arrangement increases the data read and write
stability alongside reducing the power loss and improving the data retention rate.
1: Size : 32kBits
2: Area optimized desigb
3: 95nm pdk library
| Item Name | Type | No. of Units | Per Unit Cost (in Rs) | Total (in Rs) |
|---|---|---|---|---|
| Graphic card | Equipment | 1 | 65000 | 65000 |
| Total in (Rs) | 65000 |
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