SoCNow

Designing a System on Chip (SoC) from scratch takes months to complete, sometimes years to design an efficient one. After the designing phase, Testing and verification of it is another dimension of stress. In order to save time designers prefer to re-use a verified component in their design. But thi

Project Title

SoCNow

Project Area of Specialization

Software Engineering

Project Summary

Designing a System on Chip (SoC) from scratch takes months to complete, sometimes years to design an efficient one. After the designing phase, Testing and verification of it is another dimension of stress. In order to save time designers prefer to re-use a verified component in their design. But this takes more time instead of saving it because it is quite difficult to understand the functionality and usability of a component without proper documentation, which is missing in the majority of open source contributions. That’s why a software is needed in the open source semiconductor market that can generate or design an SoC within a matter of minutes instead of taking years of the designer to completely build/design it or any designer can generate only a component with its proper documentation and it will be plug and play supported.

Project Objectives

Design a SoC. Verify SoC. Reuse the components. Generate bitstream. Test on FPGA

Project Implementation Method

First we start implementation of SoC through chisel and scala language. For this, we start implementation of core with the basic extension i.e. I extension. After testing it through self checking tests and compliance testson simulation. Make a separate module of M ,F and C extension and integerate in core then again verify these through self checking tests on simulation.Then, we start implementation of devices which includes gpio(which is basic), spi,spi flash,uart,I2C, and timer. Verify their working through simulation and fpga.Then,we start implementation of buses which includes Tilelink,wishbone and tilelink cached. Verify their working through simulation and fpga.Then make a frameworks for integration of devices and buses i.e jigsaw and caravan respectively.After complete implementation of core,devices and bus separately, we integerate all these together to generate complete SoC. Test the generate SoC on simulation and fpga.After that, we design frontend of web application. Then backend of web app using django and python scripts.For Soc gneration we create a script which automatically generate SoC according to parameters which user select.In web app, we will provide an interface to user from which he can select multiple extension for core , multiple devices and buses. Then generate RTL code.Through generated RTL, user can also create a bitstream of it. In order to generate bitstream, first user have to select FPGA board, then the IOs are mapped on xdc file, then the process of synthesize is start and after that bitstream is generated and ready to upload on FPGA board. We also provide an interface where user can write C language program for testing. User can also verify working of core through compliance test.

Benefits of the Project

The major benefit of our project exhibit that in Designing a System on Chip (SoC) will be done in no time (very minimal time) 

-Re-use a verified component is also become possible . 

-The understanding and the functionality and usability of a component with proper documentation

-An step towards open source contributions (no cost tool for generating customized/configurable SoCs )

-Designer can completely build/design desired SoC with its plug and play support.

-SoC-Now will also provide the functionality of generating just only the Core standalone.

-Any Device or any other SoC Component can also be generated separately. 

-SoC-Now contains a separate verification module with which targeted users can perform the formal verification process on the customized generated SoC, Core and/or Peripherals.

-Soc-Now will allow users to select the Field Programmable Gate Array (FPGA) of their choice from the list of supported FPGAs. Then the user shall select/configure the Input/Output (I/O) mapping on the selected FPGA Board that where (LEDs, RGB LEDs, P-Mod Headers) any output pin of the component should be displayed and from where (Buttons, Switches) the component may get any kind of input or would not get any input. 

-After that Bitsream generation process will begin in which first of all Synthesization of the generated component’s Register Transfer Level (RTL) will take place. 

-After Synthesis process, Routing and Placement of the synthesized RTL will be performed and after its completion Bitstream will be successfully generated. This entire process will be a black box for the end user, he/she will only be able to see that the Bitstream generated right after clicking on the Generate Bitstream button.

Technical Details of Final Deliverable

The final deliverable is a website, user can select multiple peripherals like UART, SPI, SPI flash, Timer and I2C. GPIO is set by default. Then user can select extension like we have M extension, C extension and F extension for now, fter that user have to select bus for communication purpose. We have 3 buses for now Wishbone, Tilelink, Tilelink cached. After selecting all these things we provide a block diagram which is basically a review diagram that what things are selected by user and by just confirming it user would get a complete RTL of the SoC. 

In addition, we also provide a interface on which user can write C program and simulate it on the SoC as well as user can run compliance test and get a report of it.

After, the RTL is generated, user can also create a bitstream of it. In order to generate bitstream, first you have to select FPGA board, then the IOs are mapped on xdc file, then the process of synthesize is start and after that your bitstream is generated and ready to upload on FPGA board.

Final Deliverable of the Project

HW/SW integrated system

Core Industry

IT

Other Industries

Core Technology

Internet of Things (IoT)

Other Technologies

Sustainable Development Goals

Quality Education, Decent Work and Economic Growth, Industry, Innovation and Infrastructure

Required Resources

If you need this project, please contact me on contact@adikhanofficial.com