RISC-V BASED 32-BIT MULTI-CYCLE PROCESSOR DESIGN

As versatility and embeddability is becoming progressively significant for various types of electronic systems, the interest for low-power microchips along with fast processing speed   is detonating. RISC-V is an instruction set architecture (ISA) which is simple, open source yet

Project Title

RISC-V BASED 32-BIT MULTI-CYCLE PROCESSOR DESIGN

Project Area of Specialization

Electrical/Electronic Engineering

Project Summary

As versatility and embeddability is becoming progressively significant for various types of electronic systems, the interest for low-power microchips along with fast processing speed   is detonating. RISC-V is an instruction set architecture (ISA) which is simple, open source yet faster.

RISC-V is not just an open source, it is also known as frozen ISA. The base instructions are frozen and accepted optional extensions are also frozen. Software and applications written for RISC-V will run on similar cores forever. Custom instructions are also provided to companies to develop products especially tailored to their workload which gives inherent security as well.

The main promoter of RISC-V is creativity. Since ISA is open, designs for low power, performance and protection etc. can be optimized while retaining full compatibility with other designs. As the hardware implementation is substantially more regulated, it provides hardware engineers with more control over the implementation of processor. They can make suggestions at a much earlier point can optimize the designs to make them power efficient.

Accordingly, to handle the power and performance of workloads, a RISC-V single-issue five-stage pipelined data path extending it up to the microprocessor is assembled dedicated to high performance computing.

There is a huge have a go in embedded applications, IoTs to automative and computer devices . We believe that this exploration can be a foundation for future investigations of more confounded microprocessor plans which issue various guidelines simultaneously and have more pipeline stages.

Project Objectives

1. A smart multi-cycle RISC-V processor design for embedded applications.

2. The main objective is to build-up RISC-V on the FPGA board implementation.

3. To enhance the performance of the multi-cycle approach is implemented.

4. Developed skilled labor with SDG.

5. To promote the digital IC design in pakistan.

6. To understand and develop the behavioural level implementation.

Project Implementation Method

I have designed third-level microprocessor by using the Hardware Description Language (Verilog). First, we have discussed about basic components of block such as combinational circuits of logic gates, Adders, subtractors, ALU, decoder and Multiplexers. For gates, Alu and Multiplexers, we have provided the Verilog code and performed simulations. Then combined these elements to construct the Datapath which is the main component of microprocessor. We also discussed about FPGA which stands for Field Programmable Gate Array, they are capable of performing complex programs. These devices are responsible for performing the operations of Digital logic signals and microcontrollers as well as implementation of general logic. After discussing the basic components and making the Dedicated Datapath or General-purpose Datapath, we have studied control units which are another essential component of the microprocessor. It is also named as Finite State Machine, as it controls the signals given to the Datapath for the execution of operations at the right time.

Finally, constructed microprocessor using the Verilog algorithm of finite state machine. Microprocessor is mainly composed of two parts, one is Datapath and other is Control unit. We’ve used this basic building technique to build up third-level microprocessor design which is composed of FSM model and uses Verilog operators to synthesize and connect FSM unit and Datapath unit together automatically. Also  constructed this model of microprocessor as it provides us the advantage of computing the operations by using Verilog rather than making it manually. The only disadvantage is that the timing of a circuit cannot be controlled as the system works automatically.

RISC-V is pronounced as Risk-five. It is an advanced version of RISC architecture. RISC-V is an open standard instruction set (ISA) which has basics of established reduced instruction set computer principles [9]. It does not requires fee to use as it has open license source.

We have designed a microprocessor with the help of RISC V architecture. We have designed single cycle microprocessor through Verilog coding.

By combining together following units we can achieve single cycle RISC-V architecture;

• Arithmetic Logic Unit
• Register File
• Memory Unit

- SRAM: Cache

- DRAM: Main memory

Benefits of the Project

1. Boost the country with digital IC design technology embedded processor.

2. Asuccessful development of its prototype on FPGA leads to design in Pakistan.

3. This will also cut the imports of the expensive equipment used in biomedical, telecommunicaiton, communication.

4. It will be avilable locally that will boost the local industry.

5. This will develop local human resource as skilled worker.

Technical Details of Final Deliverable

The complete multi-cycle RISC-V processor implemented will be simulated and finally implemented on the FPGA board for demo.

Register file has the meaning in its name as file represents the compilation of the data, in the similar way register file is the array of processor registers in the main processor called central processing unit. On the usual basis register files are implemented by way of fast static RAMs having multiple number of ports.

The main features of RISC V architecture include load-store instructions, bit patterns are used to simplify the MUXes in central processing unit, IEEE 754 floating point, and it is the neutral architecture and used to place most-significant bits at the fixed place to speed sign extension.

A processor has the registers to store the instructions which makes the Data memory. “RISC V is a load and store architecture, having instructions address only registers, with load and store instructions moving to and from memory”.

  A processor has three basic steps as follows

1. It fetches the data
2. It decodes data
3. Then it executes the data

Instruction memory is used to store the instruction then processor fetches the instruction it decodes it and executes.

Final Deliverable of the Project

HW/SW integrated system

Core Industry

Telecommunication

Other Industries

Education

Core Technology

Wearables and Implantables

Other Technologies

Internet of Things (IoT), Blockchain, Robotics, Others

Sustainable Development Goals

Good Health and Well-Being for People, Quality Education, Decent Work and Economic Growth, Industry, Innovation and Infrastructure, Responsible Consumption and Production

Required Resources

If you need this project, please contact me on contact@adikhanofficial.com