FPGA Based Hardware Accelerators for Cryptographic Algorithms

Securing the information is a key requirement in modern day communication. For this purpose different schemes and algorithms are used. As the modern computing systems evolve and become more efficient in solving complex problems, conventional data encryption schemes have become vulnerable to cyber at

Project Title

FPGA Based Hardware Accelerators for Cryptographic Algorithms

Project Area of Specialization

Cyber Security

Project Summary

Securing the information is a key requirement in modern day communication. For this purpose different schemes and algorithms are used. As the modern computing systems evolve and become more efficient in solving complex problems, conventional data encryption schemes have become vulnerable to cyber attacks. To deal with this problem, more complex and advanced encryption algorithms have been designed such as lattice based cryptographic algorithms. It is theoretically proven that these complex algorithms can resist the most advanced attacks such as those generated by a qauntum-computer.

However, the efficiency of these complex cryptographic algorithms comes at the cost of high computational complexity, therefore implementing them in real-time is a huge challenge. To meet these real-time requirements, dedicated hardware accelerators is required.

Fortunately, these algorithms are highly parallel in nature. Graphical processing units (GPUs) support parallel computing, therefore they are a go-to choice for implementing these algorithms. However, GPUs consume large amount of energy to process such complex tasks and are not cost efficient. Therefore, GPU implementations of these algorithms is not an ideal solution for use in IOT/embedded devices. On the other hand, FPGAs provide a comparable level of parallelism at much less cost and enery consumption as compared to GPUs. However, designing FPGA based accelerator of such complex algorithms is a highly demanding task.

In this project, we propose to optimize the post-quantum attack resistant cryptographic algorithms for FPGA implementation and design FPGA based dedicated hardware accelerators feasible for use in IOT/embedded devices.

Project Objectives

• The aim of the project is to design real-time hardware implementation of post-quantum attack resistant cryptographic algorithms.
• A hardware accelerator that can be used in embedded/IOT devices.
• Achieving the goal of low energy requirement for processing of cryptographic algorithms.

Project Implementation Method

In the first stage of this project, we study several existing encryption algorithms and analyze their efficiency and hardware implementation results as reported in the literature. We aim to identify the algorithms that are both secure and provide high level of parallelism. The identified algorithms will be modified to increase their suitability for FPGA implementation while maintaing their security. In this regard, so far we have currently identified Brakerski/Fan-Vercauteren (BFV) encryption scheme among homomorphic encryption and Number Theoratic Transform (NTT) for lattice based cryptography (using polynomial).

In the second phase, these algorithms will be implemented using Verilog HDL. The RTL codes will be verified using software simulation. Further optimization of the codes will be done to achieve high performance and maximum energy efficiency. The results will be compared with state-of-the-art.

Towards the end, the RTL codes will be implemented on an FPGA for proof of concept. The implementation and simulation results will be cross-verified to ensure the correctness of the design.

Benefits of the Project

This project proposes FPGA based hardware accelerators for complex cryptographic algorithms as compared to traditional GPU based implementations, therefore providing a cost and energy-efficient solution in contrast to the state-of-the-art. This solution is useful for embedded/IOT devices because in embedded devices low area and less energy consumption are the fundamental requirements along with efficient computation.

The proposed project provides a comprehensive solution for data processing and security in real-time even on small-scale systems. This ensures highest level of security against the most vulnerable attacks such as those launched by quantum-computer. 

The proposed solution can be used in a variety of applications ranging from handheld devices to highly confidential defence applications due to its efficiency and cost-effectiveness.

Technical Details of Final Deliverable

The mathematical models of the modified cryptographic algorithms and their RTL codes written in Verilog HDL will be provided, supplemented by simulation and implementation results for proof of concept. A comparartive study of results with conventional GPU implementations will also be provided outlining the advantages of the proposed scheme.

Final Deliverable of the Project

HW/SW integrated system

Core Industry

IT

Other Industries

Core Technology

Others

Other Technologies

Sustainable Development Goals

Industry, Innovation and Infrastructure

Required Resources

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