Design and Implement a 10 Gigabit Ethernet Communication Interface for High Frequency Trading on FPGAs.

This project focus on the design of an application specific hardware for accelerating High Frequency Trading applications. It is optimized to achieve the lowest possible latency for interpreting market data feeds and hence enable minimal round-trip times for executing electronic stock trades. The implementation described in this work enables hardware decoding of Ethernet, IP and UDP as well as of the FAST protocol which is a common protocol to transmit market feeds.

For this purpose, we developed a microcode engine with a corresponding instruction set as well as a compiler which enables the flexibility to support a wide range of applied trading protocols. The complete system has been implemented in RTL code and evaluated on an FPGA. Our approach shows a 4x latency reduction in comparison to the conventional Software based approach. A typical HFT system consists of four main building blocks: network stack, financial protocol parsing, order book handling and custom application layer. Financial exchanges broadcast market updates along an Ethernet connection at typical line rates of 10 Gb/s.      

The ZYNQ SoC based secure data transmission implementation in an embedded system shows that ZYNQ SoC based implementation uses less space & weight compared to Telemetry System. The high performance and lower latency plays an important role in any embedded system especially in the mission critical applications. The ZYNQ SoC supports shared memory access, it allows to achieve higher performance and lower latency in Embedded Multiprocessor based designs.

The Zynq-7000 internal architecture makes it possible to implement the custom IPs as well as logics in the PL. Also, it enables a custom software in the PS. It makes easier to develop a unique and differentiated functional systems. The PL & PS integration allows high level of performance and reliability that multi-chip based solutions (e.g. a FPGA with an ASSP) can’t afford because of their less number of I/O as well as bandwidth, latency and power requirements cum budgets.

This project talks about the data transfer interfaces available on the ZYNQ platform, data throughputs of different interface along with advantages and disadvantages of each type of communication interface.

                                                                   Figure 2– Latency vs Development Time

The main objectives of this project are

• To provide a communication logic/ interface between the PL and PS which is an essential component of ZYNQ Architecture for bi-directional data transfer.
• We will build a FPGA implementation of HFT for low latency and high throughput and see how close we can get to state of the art taking into account our constrained resources.
• HFT companies are currently moving in the direction of using FPGAs to replace their current software system.

                                                   Figure 3– Project Objective

Implementation of project involves

• First, find the best software for generating Ethernet Data packets.
• Now, we find a way to capture these generated Ethernet data packets.
• Implementation of embedded processor inside FPGA (Field Programmable Gate Array) such that it can receive Ethernet packets, extract the actual data, process it and finally transmit it to other subsystems if required.
• Now, we also have to send that data to Soft IP for that we have to study the Architecture of PL (Programming Logic) in order to interface PS with PL we must know the AXI interface.
• The software part of the processor is configured in SDK (Software Development Kit). The implementation requires ZYNQ development board, Ethernet cross cable.
• After establishing the link between the PC and development board using Ethernet interface, the commands are sent from the PC to PS through Ethernet interface.

Testing

For testing our project, first we have to implement this on PC using loop-back test on Software simulation because if we get the desired/successful result on the PC then we can easily implement the same logic and idea on the hardware also known as ZYNQ chip.

Testing of project involves the following steps;

• First of all, we generate packets on PC using Colasoft Packet Builder.
• After that, TURN ON the Wireshark capture these generated packets on the Wireshark and send it back to the PC.
• Now, if the PC received the same Ethernet generated packets successfully which it sends earlier. So, we can we say or concluded that our Loop-back test was successful and now we can try to send these Ethernet generated packets to the PS then PL using AXI interface.

The implementation described in this work enables hardware decoding of Ethernet, IP and UDP as well as of the FAST protocol which is a common protocol to transmit market feeds. It is optimized to achieve the lowest possible latency for interpreting market data feeds and hence enable minimal round-trip times for executing electronic stock trades.

                                                                                                                                                                                                     Figure 4– Block Diagram of Tri-mode Ethernet in Vivado

There are many benefits of this project for Pakistan financial and stock prediction systems as well as for local investors Some of the benefits are follow as below:

• There is a growing demand for low cost, power efficient MAC IP Core for various embedded applications. In this paper a project is discussed to design an Ethernet MAC IP Core solution for such embedded applications.
• FPGA chips have very specific technical characteristics that enable them to execute certain types of trading algorithms up to 1000 times faster than traditional software solutions.
• The key to the success of Gigabit-Ethernet resides implementation is simple in hardware and provides larger data rates than most computers can process these days.
• The Ethernet protocol has increasingly added support for different data rates and physical media, and different FPGAs implement the physical layer (including serializer and deserializer mechanisms) differently.

The final deliverables are divided into Hardware and Software components:

Software Deliverables

In our project Software Deliverables will be:

• The software part of the processor is configured in SDK (Software Development Kit).
• Colasoft Packet Builder is used for the generation of Ethernet packets.
• Wireshark is used to capture these transmission of packets.
• Vivado is used to make the logic of Ethernet IP for high speed integration.

Hardware Deliverables

        The Zynq-7000 internal architecture makes it possible to implement the custom IPs as well as logics in the PL. Also, it enables a custom software in the PS. It makes easier to develop a unique and differentiated functional systems. The PL & PS integration allows high level of performance and reliability that multi-chip based solutions (e.g. a FPGA with an ASSP) can’t afford because of their less number of I/O as well as bandwidth, latency and power requirements cum budgets.

The main objectives of this project are

• To provide a communication logic/ interface between the PL and PS which is an essential component of ZYNQ Architecture for bi-directional data transfer.
• We will build a FPGA implementation of HFT for low latency and high throughput and see how close we can get to state of the art taking into account our constrained resources.
• HFT companies are currently moving in the direction of using FPGAs to replace their current software system.

                                                   Figure 3– Project Objective