CNN acceleration on FPGA

Project Title

CNN acceleration on FPGA

Project Area of Specialization Artificial IntelligenceProject Summary

Our project is about accelerating the inference of CNN (convolutional Neural Networks) by taking advantage of extreme parallelism provided by FPGA (field programmable gate array).

Contemporary work is being done by  Xilinx /Intel and others in this field but the work is still in its infancy. We are using Zybo Z7 by Xilinx  as hardware, and currently attempting to implement SLR(sign language recognition) and Tiny Yolo architecture before moving on to other CNN architectures and making it reconfigurable.

Project Objectives

Our project objectives are:

• Implementing  CNN models in  Python,C++ as well as in Verilog
• Implementing Sign Language Recognition using Tensorflow
• Implementing Tiny Yolo using Tensorflow
• Implementing Sign Language Recognition on Zybo Z7
• Implementing Tiny Yolo on Zybo Z7
• Comparing the speed and results of models on Zybo Z7/FPGA with tensorflow implementations.

Project Implementation Method

Our project is being developed in the following fashion

#Vivado HLS (high language synthesis) uses C/C++ code

#Vivado (HDL) uses Verilog code

• Implementing/writing code for basic functions/operations for CNN models in  Python,C++ as well as in Verilog
• Implementing Sign Language Recognition using above functions in C++ and using Vivado HLS.
• Implemeting Tiny Yolo using above functions in C++ using Vivado HLS
• Implementing Sign Language Recognition using above functions in Verilog using Vivado
• Implemeting Tiny Yolo using above functions in verilog using Vivado
• Acquiring additional Data for the Sign Language recognition
• Acquiring additional Data for Object Detection
• Testing CNN models.
• Implementing SLR and Tiny Yolo in Python as well.
• Comparing the speed, accuracy and power consumption among all implementations

Benefits of the Project

This project provides Hardware Acceleration to all kinds of Deep Learning applications , be it from health, or security or whatever.

Although the user would have to invest in an FPGA, the returns would be faster inference, low power consumption as well as reconfigurability. Its ideal for applications that require faster inference/object detection without losing any Accuracy .

Technical Details of Final Deliverable

The final deliverable will be comprising of Tiny Yolo(v2) running on Zed board and Zybo with the input image 
being fed to the CNN through the MATLAB directly with the help of serial transmitter which will
be managed on zed board side by help of uart lite module. When our architecture will be fully completed
and tested, then we will compare our results with other architectures and we are also aiming to achieve
hardware acccleration with respect to CPU. Coming to GPU's, they use floating point computation while 
we will be using fixed point computation and researches have shown that fixed point computations are 
comparatively fster than floating point computations and can therefore act as a plus point for us. 

Final Deliverable of the Project HW/SW integrated systemType of Industry Manufacturing , Others Technologies Artificial Intelligence(AI), Others, Big DataSustainable Development Goals Industry, Innovation and Infrastructure, Sustainable Cities and CommunitiesRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	74500
Zybo Z7-20	Equipment	1	69000	69000
Camera	Miscellaneous	1	500	500
FPGAs for software engineer	Miscellaneous	1	5000	5000