Artificial Intelligence Accelerator

Project Title

Artificial Intelligence Accelerator

Project Area of Specialization Artificial IntelligenceProject Summary

Artificial intelligence accelerator is used to run many Machine Learning algorithms. Various hardware platforms are used to support its processing. However, there are many challenges that need to be addressed for the successful computation of these algorithms such as high computational processing, cost efficiency and low power consumption at the same time. Field Programmable Gate Array (FPGA) technology can be customized to meet the specific requirements for the implementation of ML algorithms. The use of FPGA in deep learning has seen significant increase due to its capacity for maximizing parallelism and energy efficiency. Convolutional Neural Networks (CNNs) have become the real standard by delivering good accuracy in many applications related to machine vision supported by machine learning or deep learning (e.g., classification, detection segmentation) and speech recognition. For faster and speedy results, we need to accelerate CNN algorithms. FPGA has exceptional features which make it an achiever in accelerating deep learning algorithm. The prominent features are flexibility, low latency, and high-power efficiency. Flexibility allows us to configure the hardware down to bit level. It is competitive in its features when precision is required in deep learning algorithms.

Project Objectives

Hardware acceleration has many advantages, the main being speed. Accelerators can greatly decrease the amount of time it takes to train and execute an AI model and can also be used to execute special AI-based tasks that cannot be conducted on a central processing unit (CPU) or a graphical processing unit (GPU).

The objective of the project is to design an FPGA based AI Accelerator with:

• Capability of running optimized ML algorithms.
• Less computational complexity.
• Less power consumption.

Project Implementation Method

The project is implemented as an AI accelerator on FPGA by designing a top module called ren_conv. There will be 10 to 11 ren_conv modules, connected to each other through Advanced eXtensible Interface (AXI) Bus, acting parallelly. Each ren_conv module has different sub-modules such as:

• Data path
• Address generating unit (AGU)

This ren_conv is connected to three B-RAM and configuration register.

The B-RAMs are:

• Kernel B-RAM
• Result B-RAM
• Image B-RAM  

Benefits of the Project

It has become apparent that researching, developing, and deploying Artificial Intelligence (AI) and machine learning (ML) solutions has become a promising path to addressing the challenges of evolving events, data deluge, and rapid course of action faced by many industries, militaries, and other organizations. Hardware acceleration has many advantages, the main being speed. Accelerators can greatly decrease the amount of time it takes to train and execute an AI model and can also be used to execute special AI-based tasks that cannot be conducted on a CPUs/GPUs.

Technical Details of Final Deliverable

The deliverable of the project will be such that it will be comparing a non-accelerated outcome with the accelerated one on an FPGA. Its main goal is to accelerate an AI algorithm and that will utilize less time for its computation as compared to the normal functioning. The algorithm put to test is Convolutional Neural Network (CNN). It is a deep learning algorithm which can take in an input image, assign learnable weights and biases to objects in the image and able to differentiate one from the other. It is used for image classification and recognition. It will be provided with an input image and then run the algorithm through accelerator and without accelerator. In the end, both the scenarios will be compared based on time taken and as predicted, the output through the accelerator will be faster than that without accelerator.

Final Deliverable of the Project Hardware SystemCore Industry EducationOther Industries Others Core Technology Artificial Intelligence(AI)Other Technologies OthersSustainable Development Goals Industry, Innovation and InfrastructureRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	80000
FPGA SoC Development	Equipment	1	70000	70000
Stationery, Poster Prinitng, Thesis Printing.	Miscellaneous	1	10000	10000