Assignment No 1 - History of Intel Processors, CISC & RISC Architecture
2019-03-18 13:26:53 - Adil Khan
History of Intel Processors
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S. No |
Model |
Specifications |
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1 |
Intel 4004 |
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|
2 |
Intel 4040 |
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|
3 |
Intel 8008 |
|
|
4 |
Intel 8080 |
|
|
5 |
Intel 8085 |
|
|
6 |
Intel 8086 |
|
|
7 |
Intel 8088 |
|
|
8 |
Intel 80386 |
|
|
9 |
Intel 80486 |
|
|
|
Intel Pentium |
|
|
11 |
Intel Pentium Pro |
|
|
12 |
Intel Pentium II |
|
|
13 |
Intel Pentium III |
|
|
14 |
Intel Pentium IV |
|
|
15 |
Intel Pentium Dual Core |
|
|
16 |
Intel Core i3 |
x86 and 64bit processor Introduced in 2010 Dual Core and Quad Core Up to 3.90 GHz
|
|
17 |
Intel Core i5 |
64bit processor Introduced in 2011 Quad Core and Octa Core Clock speed 1.2 - 3.60GHz
|
|
18 |
Intel Core i7 |
62 bit processor Introduced in Core 2 Quad Clock speed 1.3 to 3.60 Clock speed can be increased by providing extra power in some generations. |
What is RISC?
A reduced instruction set computer is a computer which only uses simple commands that can be divided into several instructions which achieve low-level operation within a single CLK cycle, as its name proposes “Reduced Instruction Set”.
What is CISC?
A complex instruction set computer is a computer where single instructions can perform numerous low-level operations like a load from memory, an arithmetic operation, and a memory store or are accomplished by multi-step processes or addressing modes in single instructions, as its name proposes “Complex Instruction Set”.
Difference between RISC and CISC Architecture
Difference between RISC and CISC
|
RISC |
CISC |
|
1. RISC stands for Reduced Instruction Set Computer. |
1. CISC stands for Complex Instruction Set Computer. |
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2. RISC processors have simple instructions taking about one clock cycle. The average clock cycle per instruction (CPI) is 1.5 |
2. CSIC processor has complex instructions that take up multiple clocks for execution. The average clock cycle per instruction (CPI) is in the range of 2 and 15. |
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3. Performance is optimized with more focus on software |
3. Performance is optimized with more focus on hardware. |
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4. It has no memory unit and uses a separate hardware to implement instructions. |
4. It has a memory unit to implement complex instructions. |
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5. It has a hard-wired unit of programming. |
5. It has a microprogramming unit. |
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6. The instruction set is reduced i.e. it has only a few instructions in the instruction set. Many of these instructions are very primitive. |
6. The instruction set has a variety of different instructions that can be used for complex operations. |
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7. The instruction set has a variety of different instructions that can be used for complex operations. |
7. CISC has many different addressing modes and can thus be used to represent higher-level programming language statements more efficiently. |
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8. Complex addressing modes are synthesized using the software. |
8. CISC already supports complex addressing modes |
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9. Multiple register sets are present |
9. Only has a single register set |
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10. RISC processors are highly pipelined |
10. They are normally not pipelined or less pipelined |
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11. The complexity of RISC lies with the compiler that executes the program |
11. The complexity lies in the microprogram |
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12. Execution time is very less |
12. Execution time is very high |
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13. Code expansion can be a problem |
13. Code expansion is not a problem |
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14. Decoding of instructions is simple. |
14. Decoding of instructions is complex |
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15. It does not require external memory for calculations |
15. It requires external memory for calculations |
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16. The most common RISC microprocessors are Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture, and SPARC. |
16. Examples of CISC processors are the System/360, VAX, PDP-11, Motorola 68000 family, AMD and Intel x86 CPUs. |
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17. RISC architecture is used in high-end applications such as video processing, telecommunications and image processing. |
17. CISC architecture is used in low-end applications such as security systems, home automation, etc. |
Download: Assignment No 1 - History of Intel Processors, CISC & RISC Architecture _ 0.pdf
Download: Assignment No 1 - History of Intel Processors, CISC & RISC Architecture _ 1.pdf