10x10 Bit Multiplier

Project Title

10x10 Bit Multiplier

Project Area of Specialization Electrical/Electronic EngineeringProject Summary

The requirement of high-performance processors in digital signal processing (DSP) is increasing in new communication standards and high aggregation system. The largest silicon consumers of the DSP system are multipliers required by finite impulse response (FIR) filters and other DSP functions, so an efficient implementation of multipliers is the key for the cost-effective solution of these applications. In parallel with reducing the chip area required for multiplier implementation, the multiplier speed should be maintained or even increased during realization. These two dominant factors challenge researchers to do new works to find out the best multiplier that can be used in DSP applications. Multipliers are also important in matrix multiplications, which are applied, for instance, in 3D affine transformations. Several multipliers, demonstrating several advantages, have been reported in the last few decades. Goto et al, for example, realized the regularly structured tree multiplier implemented using 0.18?m CMOS process, focusing on layout density and multiplication time. Speed consideration is another example given by Lamberti et al. who introduced a way of reducing computation time in two’s complement multipliers with short bit width. Similar work also introduced by Dimitrov et al., who have developed efficient area multipliers based on multiple-radix representations. The latter multipliers have been realized using 0.18 µm CMOS technology, and gave better area and power consumption compared to other multipliers. However, the technique is not suitable to build fast multipliers. Since the fabrication process is time consuming, an alternative approach as hardware realization is required to design hardware such multipliers. Zulhelmi: FPGA Implementation of 16-bit Multipliers based upon Vedic Mathematic Approach 167 Versi online. Hence Field Programmable Logic Arrays (FPGAs) has been developed to solve the issues.

There are different techniques for implementation, like multiplication using carry save adders, Booth and modified booth algorithum.

Project Objectives

1. A low power hardware implementation of multipler will be designed which could be integrated into bigger building block.

2. The main objective of this project is to build up low power multipler for telecommunication applications in general.

3. To understand and develop the hardware implementation of multipler using carry save adder as well as Booth alogorithm method.

4. To reduce the power consumption of the mulitpler optimized design is selected for FPGA implementation.

5. Develop skilled in students to implementaion of hardware.

6. To promote Digital Integrated-Circuit (IC) Design.

Project Implementation Method

After the multiplier algorithum is simulated in verilog then design block of the optimized code will be implemented on the FPGA  and CoolRunner 2 kit from Xilinx.

The first phase is to write the design block code of multiper of 10 x 10.

The second is to write the testbench code fo this multiplier.

After the verification at the simulation level, the code for carry save adder and also using Booth algorithum implemented.

The last step is verifcation at the hardware level, the place and route and final area constraints and timing constraints will be discussed and meet the requirement of the design.

Since FPGA has been developed to solve the issues. Prior to discovering FPGAs, multipliers have been designed and implemented on chips, as sub-systems of processors using Application Specific Integrated Circuit (ASIC). Even though the ASIC’s implementation provides the best performance of realizing hardware, a number of issues is accounted as follows. The first is that the Integrated circuit costs are rising aggressively. Then the ASIC complexity has lengthened development time. Also the R&D resources and headcount are decreasing. The revenue losses for slow time-to-market are increasing. The financial constraints in a poor economy are driving low-cost technologies. These trends make FPGAs a better alternative than ASICs for a larger number of even higher-volume applications than they have been historically used for. 

Benefits of the Project

1. Economically boost the country with digital IC designer capability.

2. A successful development of multiplier on the FPGAresults leads to design IC in pakistan.

3. This will also cut the import if this multipler can be integrated into some telecommunication product or communication devices.

4. It will be avilable locally that will boost the local industry.

5. This will develop local human resources as skilled worker.

Technical Details of Final Deliverable

The complete FPGA implementation of the multipler algorithum in telecommunication devices can achieve very small area with different techniques comparsion. The multipler performance will be compared and speed also be evulated, consider the algorithum performance.

Final Deliverable of the Project HW/SW integrated systemCore Industry TelecommunicationOther Industries Security Core Technology Wearables and ImplantablesOther Technologies BlockchainSustainable Development Goals Good Health and Well-Being for People, Decent Work and Economic Growth, Industry, Innovation and Infrastructure, Responsible Consumption and Production, Peace and Justice Strong InstitutionsRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	80000
Smart Screen	Equipment	1	35000	35000
Stationary/Printing/Coping	Miscellaneous	1	10000	10000
FPGA Kit	Equipment	1	35000	35000